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PIC32MX3XX/4XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number (1)
64-pin 100-pin
QFN/TQFP TQFP
121-pin
XBGA
Pin
Type
Buffer
Type
Description
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
PMRD
PMWR
PMALL
60
61
62
63
64
1
2
3
—
—
—
—
—
—
—
—
53
52
30
93
94
98
99
100
3
4
5
90
89
88
87
79
80
83
84
82
81
44
A4
B4
B3
A2
A1
D3
C1
D2
A5
E6
A6
B6
A9
D8
D7
C7
B8
C8
L8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
—
—
—
Parallel Master Port Data (De-multiplexed Master
mode) or Address/Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
Parallel Master Port Address Latch Enable low-byte
(Multiplexed Master modes).
PMALH
29
43
K7
O
—
Parallel Master Port Address Latch Enable high-byte
(Multiplexed Master modes).
V BUS
V USB
V BUSON
D+
D-
USBID
ENVREG
TRCLK
TRD0
TRD1
TRD2
TRD3
PGED1
34
35
11
37
36
33
57
—
—
—
—
—
16
54
55
20
57
56
51
86
91
97
96
95
92
25
H8
H9
H1
H10
J11
K10
A7
C5
A3
C3
C4
B5
K2
I
P
O
I/O
I/O
I
I
O
O
O
O
O
I/O
Analog
—
—
Analog
Analog
ST
ST
—
—
—
—
—
ST
USB Bus Power Monitor.
USB Internal Transceiver Supply.
USB Host and OTG Bus Power Control Output.
USB D+.
USB D-.
USB OTG ID Detect.
Enable for On-Chip Voltage Regulator.
Trace Clock.
Trace Data Bits 0-3.
Data I/O pin for programming/debugging
communication channel 1.
PGEC1
15
24
K1
I
ST
Clock input pin for programming/debugging
communication channel 1.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1:
Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
DS61143G-page 28
? 2010 Microchip Technology Inc.
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